| std::atomic | Intel / AMD | ARM (with LSE) |
|---|---|---|
| fetch_add() | LOCK XADD1,2,3,4,5 | LDADD1, LDADDA2, LDADDL3, LDADDAL4,5 |
| fetch_sub() | ||
| fetch_and() | LOCK AND1,2,3,4,5 | LDCLR1, LDCLRA2, LDCLRL3, LDCLRAL4,5 |
| fetch_or() | LOCK OR1,2,3,4,5 | LDSET1, LDSETA2, LDSETL3, LDSETAL4,5 |
| fetch_xor() | LOCK XOR1,2,3,4,5 | LDEOR1, LDEORA2, LDEORL3, LDEORAL4,5 |
| compare_exchange_strong() | LOCK CMPXCHG1,2,3,4,5 | CAS1, CASA2, CASL3 CASAL4,5 |
| compare_exchange_weak() |
Memory order: relaxed1, acquire2, release3, seq_cst4, acq_rel5